As is well known, to improve the speed of devices, the current technology for manufacturing semiconductor integrated circuits has succeeded in greatly reducing the resistance of interconnects and contacts of the individual devices, through the use of composite materials comprising silicon and a transition metal such as titanium or tungsten. These composite materials are termed silicides and used for forming layers with relatively low resistivity.
In particular, the formation of a silicide layer over the active areas of a MOS transistor comprises the following steps, subsequent to forming the transistor gate:
implanting first portions of the source and drain regions with dopant at a low concentration; PA1 forming spacers adjacent to the gate and interconnect lines; PA1 implanting second portions, comprised in the source and drain regions of the transistor, at a high concentration; PA1 depositing a transition metal over the entire surface of the substrate; PA1 applying a thermal process, whereby the transition metal reacts selectively with the substrate surface to yield silicide in areas not covered with dielectric.
By these process steps, the silicide deposition can be extended to also cover the polysilicon which constitutes the gates and interconnects of the transistor, since the etching steps for clearing the active areas of the oxide which overlies them have a similar effect on the interconnects formed of polysilicon lines.
However, silicide layers cannot be used in the fabrication of high voltage devices, especially HV (High Voltage) transistors of either the P-channel or the N-channel type formed by a DE (Drain Extension) technique. In these devices, the source and drain diffusions are lightly doped regions, so as to provide HV transistors with a sufficiently high breakdown voltage for operation on high bias and working voltages.
The process for producing silicide layers may develop problems on account of the light dopant concentration and small thickness of such regions. For example, during the thermal process for reacting the transition metal layer with the substrate surface, a surface layer of substrate is expended, and some dopant is taken up from the substrate by the silicide layer. Thus, in normal operation of the device, the silicide layer is shorted to the substrate.
Another problem with these high voltage transistors comes from the high strength electric fields which are created between the border of the active area of the transistor and the field oxide.
In addition, these high voltage transistors are often integrated in the same substrate as low voltage transistors. The low voltage transistors should have a short channel and have source and drain regions formed by implantations at a sufficient energy and dopant concentration to ensure retention of the source and drain regions after the formation of the silicide layer required to provide adequately fast performance of the low voltage transistors.
However, it is undesirable to increase the number of the implantations and masks used for differentiating the high voltage transistors from the low voltages ones.